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World Class Verilog & SystemVerilog Training


Unique SystemVerilog and UVM Training Opportunity
Cliff Cummings & Mark Litterick (Verilab Co-Founder) in Austin, TX


Advanced verification tools and methods such as SV and UVM offer immense potential in tackling the growing complexity in modern day chip verification. However, accessing that potential requires not only a theoretical understanding of the language and methodology, but also the practical ability to deploy them with discipline in real chip projects.

Sunburst Design and Verilab have joined forces to provide a unique training opportunity which will combine Sunburst's extensive training expertise with Verilab's experience drawn from hundreds of real world chip projects in both the USA and Europe.

The training will be conducted by Sunburst's award-winning Cliff Cummings and Verilab co-founder, Mark Litterick. Two courses will be provided: a 2-day SystemVerilog Fundamentals course, and a 3-day UVM course.

Don't miss this opportunity to learn the theory and practice of verification from two masters in the field!

Course Details

SystemVerilog Fundamentals
Location: Austin, TX
Date: Mon-Tue, April 20-21, 2015
Cost: $1,300 (Multi-engineer discount available)
Click here to register


UVM Verification
Location: Austin, TX
Date: Wed-Fri, April 22-24, 2015
Cost: $1,950 (Multi-engineer discount available)
Click here to register