World Class SystemVerilog & UVM Training
DVCon 2019 Benchmark Files: DVCON2019_BENCH_CODE.tar
Subject: Sunburst Design - DVCon 2019 - Benchmark Files
Expand the benchmark files by executing the following command:
tar xvf DVCON2019_BENCH_CODE.tar
This will create a Makefile and twelve subdirectories called BENCHM1 - BENCHM12
If you run all the benchmarks with all three simulators using the default very large Loop Count values, the simulation will probably run for ~12 hours. You can run the full simultations on each individual simulator for shorter runs. You can also change the default Loop Count values to much smaller count-values by following the instructions below. You can also run individual benchmarks by changing to the appropriate BENCHM## directories and executing the Makefiles in those directories.
From the directory with the Makefile, you can execute the following recommended Makefile options:
used to set the Loop Count values to small numbers, most equal to 100. Recommended for your first run to make sure the simulations run correctly on your computer.
These are the very large default values that I used to run the benchmark simulations.
Used to run all the benchmark simulations on just one of the simulators (Cadence, Questa, VCS).
make (or make all )
Used to run all the benchmark simulations on all three simulators
Each BENCHM## simulation will create a corresponding BENCHM##_REP (REPort) dierctory. In the report directories will be the reports for each simulation, a summary .rpt file as well as summary .csv file that I used to copy the results into an Excel spreadsheet.
The benchmark scripts are simple Makefiles that also use some SED scripting. If your company uses special commands to run the simulators, you will need to modify the simulator invocation commands inside of each BENCH##/Makefile.
I do not have time to answer all email messages regarding these benchmark scripts. Use them at your discretion.
Regards - Cliff Cummings