World Class Verilog & SystemVerilog Training

Sunburst Design - Advanced SystemVerilog for Design
by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst Design, Inc.

Cliff Cummings is the only Verilog & SystemVerilog Trainer who helped develop every IEEE & Accellera Verilog, Verilog Synthesis and SystemVerilog Standard.

Simply stated, to give engineers world class SystemVerilog language & design training using award winning materials developed by renowned Verilog & SystemVerilog Guru, Cliff Cummings

Upon completion of this course, students will:

• Write efficient synthesizable SystemVerilog-2005 RTL models
• includes new SystemVerilog data types and capabilities
• includes new SystemVerilog RTL and abstraction capabilities
• includes six different FSM coding styles
• includes multi-clock and FIFO design techniques
• Gain exposure to new SystemVerilog modeling & verifcation capabilities
• includes introduction to some new SystemVerilog Hardware Verification Language (HVL) capabilities
• includes use of dynamic types and arrays for modeling
• includes inclusion of C-models using the new SystemVerilog DPI
• includes using proven techniques for generating self-checking tests

Course Overview

Sunburst Design - Advanced SystemVerilog for Design is a 3-day fast-paced intensive course focuses new SystemVerilog features with emphasis on the new RTL & behavioral design features.

This SystemVerilog training was developed and is frequently updated by the renowned SystemVerilog guru and IEEE SystemVerilog committee member, Cliff Cummings, who has presented at numerous SystemVerilog seminars and training classes world wide, including the 2003-2004 SystemVerilog NOW! Seminars and 2004-2005 ModelSim SystemVerilog Verification Shindigs.

The 1000+ page binder and 140+ page lab guide for this 3-day course covers all of the important SystemVerilog coding styles for RTL & behavioral design. These materials are constantly being updated with the latest clarifications and corrections passed by the IEEE SystemVerilog committee, of which Cliff is an active participant. Numerous proven usage guidelines are taught and explained.

This fast-paced course teaches the new IEEE 1800-2005 advanced SystemVerilog capabilities focused mostly on RTL & behavioral design. Efficient and proven coding styles are combined with frequent exercises and insightful labs to demonstrate the power of the new SystemVerilog features. You will discover that SystemVerilog capabilities are fully backward compatible with Verilog-2001 designs and the enhancements can be used now in existing Verilog design & verification environments.

NOTE: The same course materials are used in the Sunburst Design - Advanced SystemVerilog for Design & Verification and the Sunburst Design - Advanced SystemVerilog Verification Courses.

The last three design sections of the training guide are not lectured in the Advanced SystemVerilog Verification course because there is too much material to cover in three days, but engineers still get copy of the entire SystemVerilog student guide for future reference. A 4-day version of this course is also offered by Sunburst Design for engineers who would like to also attend the lectures on Advanced SystemVerilog Design.

The course content can be modified to meet the customized needs of individual design and/or verification teams.

Target Audience

Sunburst Design - Advanced SystemVerilog for Design is intended for design engineers who require in-depth knowledge on the IEEE SystemVerilog-2005 standard with an emphasis on the new RTL & behavioral design capabilities.

Prerequisites (mandatory)

This is a very advanced SystemVerilog class that assumes engineers already have a good working knowledge of the Verilog language.

This course assumes that students have a practical working knowledge of Verilog HDL or have completed Verilog HDL training. Engineers with VHDL synthesis experience and some Verilog exposure will do well in this class. Engineers with no prior HDL training or experience will struggle in this class. Engineers with weak Verilog knowledge or experience should consider adding the 1-day, Sunburst Design - Accelerated Introduction to Verilog-2001 & Best Known Coding Practices course to fully prepare for advanced SystemVerilog training.

The Sunburst Design - Advantage

Who is teaching your "expert" and "advanced" classes? Most companies will not tell you because their instructors might not have much design experience or may never have participated on any of the Verilog Standards groups or presented at industry recognized conferences. Go to our web site and read about the Sunburst Design - Instructors - they are simply the best at what they do and they have the experience and qualifications to offer best-in-class training.

Sunburst Design Courses:

• Sunburst Design - Advanced SystemVerilog for Design & Verification - 4 days
• Sunburst Design - Advanced SystemVerilog for Design - 3 days
• Sunburst Design - Advanced SystemVerilog for Verification - 3 days
• Sunburst Design - Expert Verilog-2001 for Synthesis & Verification - 4 days
• Sunburst Design - Expert Verilog-2001 RTL Synthesis Coding - 2 days
• Sunburst Design - Expert Verilog-2001 FSM, Multi-Clock Design & Verification Techniques - 2 days
• Sunburst Design - Comprehensive Verilog-2001 Design & Best Coding Practices - 4 days
• Sunburst Design - Introduction to Verilog-2001 & Best Coding Practices - 2 days
• Sunburst Design - Advanced Verilog-2001 Knowledge & Design Practices - 2 days
• Sunburst Design - Accelerated Introduction to Verilog-2001 & Best Known Coding Practices - 1 day
• Advanced Verilog PLI Courses - (taught by a Sunburst Design training partner)

Course Customization? - Sunburst Design courses can be customized to include your company's coding guidelines or to modify the course for a different audience. Sections can be added or deleted from a course to meet you company's needs.

Course Syllabus

Day One

SystemVerilog Enhancements & Methodology Overview
- Includes a quick review of SystemVerilog resources available to design & verification engineers.

• SystemVerilog Books & Resources
• Verilog & SystemVerilog Keywords
• Verilog & SystemVerilog Enhancements
• SystemVerilog High-Level Methodology

Data Types & Typedefs
- Includes data types, enumerated types, compilation units, packages, and casting.

• Nets & Variables Fundamentals
• Blocking & Nonblocking Assignment Fundamentals
• SystemVerilog data types
• Resolved & Unresolved types
• 4-state & 2-state types
• Typedefs
• Near-Universal types
• SystemVerilog data type strategies
• Enumerated types
• $unit & $root
• Compilation units & separate compilation
• Packages & :: (package scope operator)
• SystemVerilog package strategies
• Enhanced literal numbers syntax
• Constants & Strings
• Type-casting
• Type parameters
• Jump-Start into SystemVerilog Features
• Simulation command aliases & switch definitions
• LABS: Multiple SystemVerilog types, typedefs and tape-casting labs

Logic-Specific Processes, functions, tasks
- New always_type blocks help RTL designers. Enhancements to tasks and functions make them more useful and easier to use.

• Labs review
• always_comb
• always_latch
• always_ff
• always @* -vs- always_comb
• Void functions
• always_comb & void functions
• Combinational sensitivity
• Design encapsulation through void functions
• Dual data-rate logic modeling
• New SystemVerilog operators
• Enhanced loops & jumping statements
• Auto-increment, auto-decrement
• New SystemVerilog fork-join processes
• `timescale directive
• SystemVerilog timeunit & timeprecision
• SystemVerilog enhancements to tasks
• SystemVerilog enhancements to functions
• * LABS: simple SystemVerilog combinational and sequential logic labs

Arrays, Unions, Structures & Implicit Port Instantiation
- Packed & unpacked arrays, unions and structs allow greater abstraction and more concise coding. Implicit port connections can reduce top-level ASIC and FPGA coding efforts by more than 70% and simultaneously enforce greater port type checking.

• Labs review
• Data organization
• Packed & unpacked arrays
• Array indexing
• Structs & packed structs
• Unions & packed unions
• Verilog-2001 positional & named ports
• SystemVerilog .* implicit ports
• SystemVerilog .name implicit ports
• Implicit port connection rules & comparisons - includes IEEE 1800 latest updates
• Strong port-type checking
• New debugging techniques
• Block-level testbenches with implicit ports
• Advantages & disadvantages
• LABS: implicit port instantiation labs

Nonblocking Assignments, Race Conditions & SystemVerilog Event Scheduling
- SystemVerilog is fully backward compatible with Verilog-2001. This means that SystemVerilog is fully race backward compatible. This section describes in detail how the new SystemVerilog event scheduling works and how it will reduce race conditions between RTL designs and verification suites.

• Labs review
• Verillog-2001 Event Scheduling
• 8 guidelines for RTL coding & nonblocking assignments
• SystemVerilog enhanced scheduling - includes IEEE 1800 latest updates
• Verilog -vs- SystemVerilog race conditions
• Scheduling of new SystemVerilog commands
• * Blocking & Nonblocking Assignment Details
• * Mixed RTL & Gate simulations

Day Two - (Not lectured in the SystemVerilog for Design Class)

Clocking & Program Blocks & Hardware Verification Language
- System Verilog's new built-in hardware verification language capabilities are detailed and how clocking and program blocks facilitate testing is explored.

• Testbench stimulus/verification vector timing
• Final blocks
• Verification event scheduling
• #1step
• Clocking blocks
• Clocking skews
• Default clocking block cycles
• Program blocks
• Program block interaction with the DUT

Classes, Class Methods, Virtual Classes & Virtual Methods
- Object oriented programming using classes and constrained random variables for the construction of powerful verification environments are described in this section.

• SystemVerilog class basics
• Class inheritance and extension
• Procedural programming -vs- object oriented programming
• Chaining new() constructors - illegal new() constructors
• Overloading class methods
• Working with objects
• super & this keywords
• Extending class methods
• local & protected keywords
• Virtual classes
• Virtual class methods
• LABS: classes, methods & class extension

Constrained Random Testing & Functional Coverage
- Random variables & constrained random testing are important HVL enhancements to SystemVerilog to assist the verification task. Functional coverage enables engineers to verify what has already been tested and to focus additional stimulus generation to meet untested functionality.

• Randomness
• Directed -vs- random testing
• rand & randc class types
• randcase
• randomize
• Constraints
• Important constraint rules
• Constraint distribution & membership - dist & inside
• Constraint distribution operators
• Constraint restrictions
• External constraints
• Covergroups
• Coverpoints
• Coverage capabilities
• LABS: random variables and randomization, constrained random stimulus

Day Three

SVA - SystemVerilog Assertions
- This section details how SystemVerilog syntax works and how assertions can be used for design and verification.

• Labs review
• What is an assertion?
• Assertion benefits - bug detection efficiency
• Who should add assertions?
• Assertion methodologies - key techniques & best practices
• SystemVerilog assertion types
• Overlapping & Non-overlapping implication operators
• Properties and assert property
• Overlapping & nonoverlapping implications
• Sequences
• Vacuous success
• Property styles
• Edge testing and sampled functions
• Binding SVA to an existing model
• Sampled values
• Assertion severity tasks
• SystemVerilog assertion system functions
• Assertion binding
• LABS: SystemVerilog Assertions with synchronous FIFO design

Interfaces
- Interfaces are a powerful new form of abstraction and this section details how they work for design and verification.

• Labs review
• Interface usage overview
• Introduction to generic interfaces
• Interfaces -vs- records
• How interfaces work
• 5 requirements for good interface usage
• Interfaces - legal & illegal usage
• Interface constructs
• Interface modports
• Generic interfaces
• Interfaces with testing capabilities
• * Interfaces -vs- hierarchical references
• LABS: multiple interface and interface-protocol labs

SystemVerilog Dynamic Arrays
- The new dynamic array types facilitate behavioral modeling and verification environments. SystemVerilog's new dynamic arrays are described.

• Dynamic arrays & methods
• foreach loop
• Associative arrays & methods
• Queues & concatenation operations
• Queue methods
• Semaphores & methods
• Interesting semaphore key usage
• Mail boxes & methods
• Bounded & unbounded mailboxes
• Mailboxes -vs- queues
• Semaphores & mailboxes

DPI - Direct Programming Interface - SystemVerilog's C-Language Interface
- The new Direct Programming interface (DPI) can be used to simulate C-code with SystemVerilog code. This section describes how this can be done and how DPI programming differs from PLI programming.

• DPI layers
• function import
• function export
• task export
• Using SystemVerilog simulation timing in a C model
• DPI -vs- PLI example
• No PLI required
• How to compile and simulate C-code with SystemVerilog designs
• SystemVerilog & SystemC
• LAB: SystemVerilog using C-code functions

Day Four

SystemVerilog FSM Design Techniques
- Six different FSM coding styles, enhanced with new SystemVerilog constructs, are detailed and compared for coding and synthesis efficiency.

• Moore & Mealy
• Binary & Onehot
• Review proven FSM coding styles
• One always block - avoid this
• Two always blocks - recommended
• Three always blocks - recommended
• Onehot case(1'b1) - recommended
• Onehot parameters - avoid this
• Output encoded - recommended
• Coding & synthesis efficiency
• Verilog-2001 FSM enhancements
• SystemVerilog FSM enhancements
• Advanced enumerated types
• LABS: SystemVerilog FSM design labs

Multi-clock & FIFO Design Techniques using SystemVerilog
- Detailed material for efficient implementation of multi-clock & FIFO designs.

• Metastability
• Multi-clock synthesis strategies
• Multi-signal clock crossing
• Multi-clock simulation issues
• Multi-clock FIFO design

Unique & Priority - full_case & parallel_case
- This section details how unique and priority are new SystemVerilog replacements for the dangerous "Evil Twins," full_case parallel_case.

• full_case parallel_case, "the Evil Twins"
• What is full_case?
• What is parallel_case?
• Unique & priority case
• Unique & priority if
• * Multiple small synthesis examples

Classroom Details
Training is generally conducted at your facilities. For maximum effectiveness, we recommend having one workstation or PC for every two students, with licenses for your preferred Verilog simulator (we often can help provide the simulator and temporary training licenses).

For more information, contact:
Cliff Cummings - cliffc@sunburst-design.com - Sunburst Design, Inc. - 503-641-8446