World Class Verilog & SystemVerilog Training
Sunburst Design - SystemVerilog Fundamentals
by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst Design, Inc.
|2-Day SystemVerilog Fundamentals Syllabus in PDF|
70% Lecture, 30% Lab
Introduce engineers to world class SystemVerilog language capabilities using award winning materials developed by renowned Verilog & SystemVerilog Guru, Cliff Cummings
Upon completion of this course, students will understand:
Sunburst Design - SystemVerilog Fundamentals is a 2-day fast-paced intensive course that introduces new SystemVerilog features for design, simulation and synthesis. Efficient and proven coding styles are combined with frequent exercises and insightful labs to demonstrate the capabilities of new SystemVerilog features. You will discover that SystemVerilog capabilities are fully backward compatible with Verilog-2001 designs.
This SystemVerilog training was developed and is frequently updated by the renowned SystemVerilog guru and IEEE SystemVerilog committee member, Cliff Cummings, who has presented at numerous SystemVerilog seminars and training classes world wide, including the 2003-2004 SystemVerilog NOW! Seminars and 2010 ModelSim SystemVerilog Assertion Based Verification Seminars.
Sunburst Design - SystemVerilog Fundamentals is intended for design & verification engineers who require an introduction to IEEE SystemVerilog-2005 capabilities.
This course assumes that students have a practical working knowledge of Verilog HDL or have completed Verilog HDL training. Engineers with VHDL synthesis experience and some Verilog exposure will do well in this class. Engineers with no prior HDL training or experience will struggle in this class.
Training is generally conducted at customer facilities and is sometimes offered as an open-enrollment training class. For maximum effectiveness, it is recommended to have one workstation or PC for every two students, with your preferred SystemVerilog simulator licenses (we often can help provide the simulator and temporary training licenses).
SystemVerilog Enhancements & Methodology Overview
- Includes a quick review of SystemVerilog resources available to design & verification engineers.
Data Types & Typedefs
- Includes data types, enumerated types, compilation units, packages, casting and randomization functions.
SystemVerilog Operators, Loops, Jumps. Intro to Logic-Specific Processes, Enhanced functions & tasks
- New always_type blocks help RTL designers. To help verification engineers understand design constructs, the always_type blocks are briefly introduced in this section. Enhancements to tasks and functions make them more useful and easier to use.
Implicit .* and .name Port Instantiation
- Implicit port connections can reduce top-level ASIC and FPGA coding efforts by more than 70% and simultaneously enforce greater port type checking.
Nonblocking Assignments, Race Conditions & SystemVerilog Event Scheduling
- SystemVerilog is fully backward compatible with Verilog-2001 (it is also fully race backward compatible!) This section describes in detail how the new SystemVerilog event scheduling works and how it will reduce race conditions between RTL designs and verification suites.
Structs, Unions, Packed & Unpacked Arrays
- Packed & unpacked arrays, unions and structs allow greater abstraction and more concise coding. The new dynamic array types facilitate behavioral modeling and assist in the development of verification environments.
- Interfaces are a powerful new form of abstraction and this section details how they work for design and verification. This section also discusses when and when not to use interfaces. Virtual interfaces are described after the introduction of virtual classes and virtual methods on day three.
DPI - Direct Programming Interface - SystemVerilog's C-Language Interface
(Optional section - may be omitted to give more time to other topics and labs)
- The Direct Programming Interface (DPI) can be used to simulate C-code with SystemVerilog code. This section describes how this can be done and how DPI programming differs from PLI programming.
SVA - SystemVerilog Assertions
- This section details how the SystemVerilog Assertion (SVA) syntax works and how assertions can be used for design and verification. Special macro-techniques are shown to reduce assertion coding effort by up to 80%.
For more information, contact:
Cliff Cummings - firstname.lastname@example.org - Sunburst Design, Inc. - 503-641-8446