World Class Verilog & SystemVerilog Training
Sunburst Design - Advanced SystemVerilog for Design & Verification
by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst Design, Inc.
|4-Day SystemVerilog Syllabus in PDF|
70% Lecture, 30% Lab
Make design and verification engineers productive using SystemVerilog using award winning materials developed by renowned Verilog & SystemVerilog Guru, Cliff Cummings.
Upon completion of this course, students will:
Sunburst Design - Advanced SystemVerilog for Design & Verification is a 4-day fast-paced intensive course that focuses on new and advanced design and verification features of SystemVerilog.
*NEW* - Enhanced Verification Flow - Based on seven years of teaching SystemVerilog, Sunburst Design has discovered that it is best to teach object-oriented class-based verification concepts early and often. Day-1 - includes Classes & Randomization (with labs) / Day-2 includes Constrained Random Variables in classes, Functional Coverage, Virtual Classes & Methods (with labs) / Day-3 includes Virtual Interfaces (with labs) and optional OVM fundamentals (with optional labs). When properly taught, these topics are not difficult but because they are new, it takes time and practice doing multiple labs for the concepts to be mastered.
This SystemVerilog training was developed and is frequently updated by the renowned SystemVerilog guru and IEEE SystemVerilog committee member, Cliff Cummings, who has presented at numerous SystemVerilog seminars and training classes world wide, including the 2003-2004 SystemVerilog NOW! Seminars and 2004-2005 ModelSim SystemVerilog Verification Shindigs.
The 1000+ page binder and 190+ page lab guide for this 4-day course covers all of the important SystemVerilog coding styles for design and verification. These materials are constantly being updated with the latest clarifications and corrections passed by the IEEE SystemVerilog committee, of which Cliff is an active participant. Numerous proven usage guidelines are taught and explained.
This fast-paced course teaches the IEEE 1800 advanced SystemVerilog capabilities for both design and verification tasks. Efficient and proven coding styles are combined with frequent exercises and insightful labs to demonstrate the power of the new SystemVerilog features. You will discover that SystemVerilog capabilities are fully backward compatible with Verilog-2001 designs.
The course content can be modified to meet the customized needs of individual design and/or verification teams.
Sunburst Design - Advanced SystemVerilog for Design & Verification is intended for all design & verification engineers who require in-depth knowledge on the IEEE SystemVerilog-2005 standard. This course has been updated to include optional OVM fundamentals (with labs) for verification engineers that plan to use OVM.
This is a very advanced SystemVerilog class that assumes engineers already have a good working knowledge of the Verilog language.
This course assumes that students have a practical working knowledge of Verilog HDL or have completed Verilog HDL training. Engineers with VHDL synthesis experience and some Verilog exposure will do well in this class. Engineers with no prior HDL training or experience will struggle in this class. Engineers with weak Verilog knowledge or experience should consider adding the 1-day, Sunburst Design - Accelerated Introduction to Verilog-2001 & Best Known Coding Practices course to fully prepare for advanced SystemVerilog training.
The Sunburst Design - Advantage
Who is teaching your "expert" and "advanced" classes? Most companies will not tell you because their instructors might not have much design experience or may never have participated on any of the Verilog of SystemVerilog Standards groups or presented at industry recognized conferences. Go to our web site and read about the Sunburst Design - Instructors - they are simply the best at what they do and they have the experience and qualifications to offer world-class training.
Sunburst Design Courses:
Course Customization? - Sunburst Design courses can be customized to include your company's coding guidelines or to modify the course for a different audience. Sections can be added or deleted from a course to meet you company's needs.
SystemVerilog Enhancements & Methodology Overview
- Includes a quick review of SystemVerilog resources available to design & verification engineers.
Data Types & Typedefs
- Includes data types, enumerated types, compilation units, packages, casting and randomization functions.
SystemVerilog Operators, Loops, Jumps. Intro to Logic-Specific Processes, Enhanced functions & tasks
- New always_type blocks help RTL designers. To help verification engineers understand design constructs, the always_type blocks are briefly introduced in this section. Enhancements to tasks and functions make them more useful and easier to use.
Classes, Class Variables & Randomization of Class Variables
- Object oriented programming using classes and constrained random variables for the construction of powerful verification environments are described in this section.
Nonblocking Assignments, Race Conditions & SystemVerilog Event Scheduling
- SystemVerilog is fully backward compatible with Verilog-2001 (it is also fully race backward compatible!) This section describes in detail how the new SystemVerilog event scheduling works and how it will reduce race conditions between RTL designs and verification suites.
Implicit .* and .name Port Instantiation
- Implicit port connections can reduce top-level ASIC and FPGA coding efforts by more than 70% and simultaneously enforce greater port type checking.
- Interfaces are a powerful new form of abstraction and this section details how they work for design and verification. This section also discusses when and when not to use interfaces. Virtual interfaces are described after the introduction of virtual classes and virtual methods on day three.
Constrained Random Variables, Functional Coverage and Virtual Classes, Methods and Interfaces
- Random variables & constrained random testing are important HVL enhancements to SystemVerilog to assist the verification task. Functional coverage enables engineers to verify what has already been tested and to focus additional stimulus generation to meet untested functionality.
OVM - Introduction & Fundamentals (Optional)
- Optional verification lecture topic with labs - best to add a 4th day to the verification flow for adequate lecture and lab time.
- The Open Verification Methodology (OVM) is a class-based methodology for constructing and executing high-level verification suites. This section teaches the fundamentals and functionality of OVM
Program Blocks & Clocking & Hardware Verification Language
- SystemVerilog's new built-in Hardware Verification Language (HVL) capabilities are detailed and how program and clocking blocks facilitate testing is explored.
Structs, Unions, Packed & Unpacked Arrays, Semaphores & Mailboxes
- Packed & unpacked arrays, unions and structs allow greater abstraction and more concise coding. The new dynamic array types facilitate behavioral modeling and assist in the development of verification environments. Semaphores and mailboxes are sometimes used in advanced verification methodologies such as OVM and VMM
DPI - Direct Programming Interface - SystemVerilog's C-Language Interface
(Optional section - may be omitted to give more time to other topics)
- The Direct Programming Interface (DPI) can be used to simulate C-code with SystemVerilog code. This section describes how this can be done and how DPI programming differs from PLI programming.
SVA - SystemVerilog Assertions
- This section details how the SystemVerilog Assertion (SVA) syntax works and how assertions can be used for design and verification. Special macro-techniques are shown to reduce assertion coding effort by up to 80%.
Day Four - (Not lectured in the 3-Day SystemVerilog for Verification Class)
Logic Specific Processes, Unique & Priority - full_case & parallel_case
- The new always_type blocks show design intent and help ensure construction of proper hardware designs. The always_type blocks are discussed in detail in this section. This section also details how unique and priority are new SystemVerilog replacements for the dangerous "Evil Twins," full_case parallel_case.
SystemVerilog FSM Design Techniques
- Six different FSM coding styles, enhanced with new SystemVerilog constructs, are detailed and compared for coding and synthesis efficiency. Multiple FSM designs are benchmarked for coding style efficiency.
Multi-clock Clock Domain Crossing (CDC) & FIFO Design Techniques using SystemVerilog
- Very advanced design techniques from Cliff's award-winning presentations on the efficient implementation of multi-clock CDC & FIFO designs. These materials are not specific to SystemVerilog but solutions are shown using SystemVerilog syntax (advanced techniques that all design engineers should know - the stuff you did not learn in college).
Training is generally conducted at your facilities. For maximum effectiveness, we recommend having one workstation or PC for every two students, with your preferred SystemVerilog simulator licenses (we often can help provide the simulator and temporary training licenses).
For more information, contact:
Cliff Cummings - email@example.com - Sunburst Design, Inc. - 503-641-8446