World Class Verilog & SystemVerilog Training
Sunburst Design - Comprehensive Verilog-2001 Design & Best Coding Practices
by Recognized Verilog & SystemVerilog Guru, Cliff Cummings of Sunburst Design, Inc.
Cliff Cummings is the only Verilog & SystemVerilog Trainer who helped develop every IEEE & Accellera Verilog, Verilog Synthesis and SystemVerilog Standard.
|4-Day Verilog Syllabus in PDF|
50% Lecture, 50% Lab
Basic - Intermediate Level
Simply stated, to give engineers world class Verilog training using award winning materials developed by renowned Verilog & SystemVerilog Guru, Cliff Cummings
Upon completion of this course, students will:
Sunburst Design - Comprehensive Verilog-2001 Design & Best Coding Practices is a 4-day fast-paced intensive course on the IEEE 1364-2001 Verilog Hardware Description Language and its usage for hardware design and verification. This course is designed to emphasize important RTL modeling and efficient testbench techniques while teaching the full Verilog-2001 syntax. Unlike traditional Verilog courses that start with gate-level design and work towards behavioral coding styles, the Comprehensive Verilog-2001 Design course focuses on important behavioral design and synthesis coding styles first, along with high-level verification techniques, to instill and reinforce good coding habits early and often during the entire 4-day course.
This course includes 40+ slides and a copy of Cliff's first award winning paper on nonblocking assignments to offer a comprehensive introduction to blocking vs. nonblocking assignments along with important coding guidelines related to design styles aimed at preventing Verilog simulation race conditions.
Another 40+ slides help to demonstrate multiple efficient Finite State Machine (FSM) coding styles. An EISA bus arbiter lab is designed to reinforce FSM concepts developed in class (no silly traffic-light controllers or soda pop change machines in this course!)
A detailed 700+ page student guide and 49-page Verilog-2001 HDL Quick Reference Guide supplement the lecture and provide excellent resources for after-class reference. Numerous exercises and labs reinforce the principles presented, with about 50% of class time devoted to lab work, culminating with a 5-hour final DSP design lab on the last day of class. The final lab utilizes all of the techniques learned in earlier labs and reinforces how all aspects of Verilog are used in a large design project.
Sunburst Design - Comprehensive Verilog-2001 Design & Best Coding Practices is intended for new and self-taught Verilog design and verification engineers that require a full knowledge of the capabilities of the Verilog-2001 language. This is both a design and language class. This course also fulfills all of the prerequisites for the Sunburst Design - Advanced Verilog-2001 for Synthesis & Verification course; a course that focuses specifically on Verilog-2001 techniques for design, synthesis and advanced verification.
A knowledge of digital design engineering. The ability to create files and efficiently use the editors on the operating system used in labs. Without the above skills, students cannot fully benefit from this course. Students will be writing Verilog models for basic and advanced digital circuits such as adders, multiplexers, flip-flops, and shift registers, barrel shifters and a simple DSP processor.
The Sunburst Design - Advantage
Who is teaching your "expert" and "advanced" classes? Most companies will not tell you because their instructors might not have much design experience or may never have participated on any of the Verilog Standards groups or presented at industry recognized conferences. Go to our web site and read about the Sunburst Design - Instructors - they are simply the best at what they do and they have the experience and qualifications to offer best-in-class training.
Sunburst Design Courses:
Course Customization? - Sunburst Design courses can be customized to include your company's coding guidelines or to modify the course for a different audience. Sections can be added or deleted from a course to meet you company's needs.
Overview of Verilog Resources
Introduction to Verilog Modeling
- An introduction and overview of major Verilog-2001 modeling basics.
Verilog HDL Syntax & Semantics
- Detailed instruction of important Verilog-2001 (V2K1) language syntax.
Design Verification & Running Simulations
- An introduction to writing Verilog testbenches and running Verilog simulations.
* Course notes are printed with detailed instructions on how to use the major Verilog simulators (NC Verilog, VCS, ModelSim, Questa - note: per Cadence, Verilog-XL does not and will not support Verilog-2001 enhancements).
Continuous Assignments & Operators
- Detailed discussion of continuous assignments with design examples, followed by an overview of Verilog-2001 operators, also with examples.
Programming Statements & Timescales
- Detailed discussion of blocking and nonblocking assignments, followed by an overview of Verilog-2001 programming statements with examples. This section concludes with a discussion of Verilog timescales and their impact on simulation efficiency.
Combinational Logic Modeling
- Behavioral & synthesizable coding styles for modeling combinational logic. Includes multiple Verilog-2001 enhancements.
Sequential Logic Modeling
- Behavioral & synthesizable coding styles for modeling sequential logic
RAM and ROM Modeling
- Behavioral coding styles for modeling RAMs and ROMs
- How to construct a hierarchical Verilog netlist.
Blocking vs. Nonblocking Assignments
- Detailed instruction about Verilog blocking and nonblocking assignments. Detailed description of how the Verilog event queue works. Coding guidelines using blocking & nonblocking assignments. After using blocking and nonblocking assignments for two days, now we are ready to give the details for the guidelines already presented.
State Machine Design
- Detailed description and guidelines for coding Verilog state machines.
File I/O & Testbench Development
- Description of Verilog file I/O commands and usage. Fundamentals of using Verilog file I/O within test environments. Fundamentals of developing self-checking testbenches. Includes a detailed description of stimulus and verification timing.
Verilog Synthesis Design Flows
- This section details how designs are verified, both functionally and for correct timing. Synthesis design flows are also shown for ASICs and FPGAs.
Behavioral Commands & Verilog Strengths
- This section details advanced behavioral commands that are sometimes used and abused in models and testbenches. Correct and incorrect usage examples are included.
Gate & User Defined Primitives (UDPs)
- For comprehensive coverage of the Verilog language, gate primitives and UDPs are taught in this section. Many vendors use these two primitive types to accurately model their library primitives.
- What all engineers should know to examine and use ASIC, FPGA and other vendor libraries. How path delays and timing checks are built into vendor models.
- For comprehensive coverage of the Verilog language, switch and strength reducing primitives are taught in this section. This section also details how switch primitives and strengths can be used to model passive devices, such as resistors and power supplies for board-level simulation.
Verilog Wizardry (Lab Intensive Project)
- This is the final project for the course. Students will use all aspects of the Verilog language in an actual design flow. Students will draw upon what they have learned in the previous three days to model, simulate and verify a complete Digital Signal Processor design.
Training is generally conducted at your facilities. For maximum effectiveness, we recommend having one workstation or PC for every two students, with licenses for your preferred Verilog simulator (we often can help provide the simulator and temporary training licenses).
For more information, contact:
Cliff Cummings - firstname.lastname@example.org - Sunburst Design, Inc. - 801-960-1996