Cliff-Note #1	The Sunburst Design - "Where's Waldo" Principle of Verilog Coding	Rev 1.0 - Mar 2007
Cliff-Note #2	Common Mistakes In Technical Texts	Rev 1.1 - Mar 2009
Cliff-Note #3	Are Advanced Verification Methodologies Required to Test FPGA Design?	Rev 1.0 - Nov 2012

DAC 2009	SystemVerilog-2009 Update - Part 1 - Cliff Cummings - DAC Slides - (print) SystemVerilog-2009 Update - Part 2 - Stu Sutherland - DAC Slides	Rev 1.1 Aug 2009
DAC 2008	SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification	Rev 1.1 Nov 2008
DesignCon 2005	SystemVerilog Implicit Port Connections - Simulation & Synthesis	Rev 1.2 Apr 2005
DVCON 2011	OVM & UVM Techniques for Terminating Tests	Rev 1.1 Mar 2011
DVCON 2003	The IEEE Verilog-2001 Simulation Tool Scoreboard	Rev 1.2 Apr 2003
HDLCON 2002	New Verilog-2001 Techniques for Creating Parmeterized Models (or Down With `define and Death of a defparam!)	Rev 1.2 May 2002
HDLCON 2002	SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL Modeling	Rev 1.1 Apr 2002
HDLCON 2001	Verilog-2001 Behavioral and Synthesis Enhancements	Rev 1.3 Apr 2002
HDLCON 2000	A Proposal To Remove Those Ugly Register Data Types From Verilog	Rev 1.1 Mar 2001
HDLCON 1999	Correct Methods For Adding Delays To Verilog Behavioral Models	Rev 1.1 Mar 2001
SNUG 2012 (Silicon Valley)	The OVM/UVM Factory & Factory Overrides How They Work - Why They Are Important	Rev 1.1 Jan 2013
SNUG 2009 (San Jose)	SystemVerilog Assertions Design Tricks & SVA Bind Files	Rev 1.0 Mar 2009	Voted Best Paper 1st Place
SNUG 2008 (Boston)	Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog	Rev 1.0 Nov 2008	Voted Best Paper 1st Place
SNUG 2007 (Boston)	SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification	Rev 1.1 Nov 2007	Voted Best Paper 1st Place
SNUG 2006 (Boston)	SystemVerilog Event Regions, Race Avoidance & Guidelines	Rev 1.1 Sep 2006	Important Updates November 2007
SNUG 2005 (Israel)	SystemVerilog's priority & unique - A Solution to Verilog's "full_case" & "parallel_case" Evil Twins!	Rev 1.0 Jan 2005
SNUG 2004 (Boston)	SystemVerilog 2-State Simulation Performance & Verification Advantages	Rev 1.0 Sep 2004
SNUG 2003 (Boston)	SystemVerilog - Is This The Merging of Verilog & VHDL?	Rev 1.1 Sep 2003	Voted Best Paper 3rd Place
SNUG 2003 (Boston)	Asynchronous & Synchronous Reset Design Techniques - Part Deux	Rev 1.1 Sep 2003
SNUG 2003 (San Jose)	Synthesizable Finite State Machine Design Techniques Using the New SystemVerilog 3.0 Enhancements	Rev 1.1 Mar 2003	Voted Best Paper 2nd Place
SNUG 2002 (Boston)	Verilog Nonblocking Assignments With Delays, Myths & Mysteries	Rev 1.3 Dec 2002	Voted Best Paper 2nd Place
SNUG 2002 (San Jose)	Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons	Rev 1.1 Apr 2002	Voted Best Paper 1st Place
SNUG 2002 (San Jose)	Simulation and Synthesis Techniques for Asynchronous FIFO Design	Rev 1.1 Apr 2002
SNUG 2002 (San Jose)	Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use?	Rev 1.1 Apr 2002
SNUG 2001 (San Jose)	Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs	Rev 1.1 Mar 2001	Voted Best Paper 3rd Place
SNUG 2000 (Boston)	Coding And Scripting Techniques For FSM Designs With Synthesis-Optimized, Glitch-Free Outputs	Rev 1.2 May 2002	Voted Best Paper 2nd Place
SNUG 2000 (San Jose)	Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!	Rev 1.3 Sep 2009	Voted Best Paper 1st Place
SNUG 1999 (Boston)	"full_case parallel_case", the Evil Twins of Verilog Synthesis	Rev 1.1 Oct 2000	Voted Best Paper 1st Place
SNUG 1999 (San Jose)	RTL Coding Styles That Yield Simulation and Synthesis Mismatches	Rev 1.1 Oct 2000
SNUG 1999 (San Jose)	fsm_perl: A Script to Generate RTL Code for State Machines and Synopsys Synthesis Scripts	Rev 1.1 Sep 2001	fsm_perl script temporarily unavailable
SNUG 1998 (San Jose)	State Machine Coding Styles for Synthesis	Rev 1.1 Sep 2002
ICU 2002	The Fundamentals of Efficient Synthesizable Finite State Machine Design using NC-Verilog and BuildGates	Rev 1.1 Jul 2002	Voted Best Paper 2nd Place - IC SIG
ICU 1997	Verilog Coding Styles For Improved Simulation Efficiency	Rev 1.1 Jan 2002	Voted Best Paper 1st Place - CAE SIG
ICU 1993	Passive Device Verilog Models For Board And System-Level Digital Simulation	Rev 1.1 Oct 2004

Published Papers (not yet available for download)